1. Field of the Invention
This invention relates to a process of manufacturing a semiconductor device, and more particularly to a process of manufacturing a semiconductor device which includes an ion implantation step.
2. Description of the Prior Art
Ion implantation is indispensable as a method of doping impurities in the process of manufacturing semiconductor integrated circuits and is employed in the process of manufacturing MOS ICs for formation of the channel stopper of an isolation zone, for control of threshold voltage, for formation of a source-drain and so forth. It is advantageous, particularly in formation of a self-aligned source-drain, that ions can be implanted in a self-aligned condition with a gate electrode made of polycrystalline silicon or the like.
An ion implanting step in formation of a source-drain of a CMOS IC according to the prior art will be described with reference to FIG. 1A and 1B which is a sectional view of FIG. 1A along the line A-B.
First, N-well 2 is formed on P type silicon substrate 1 as shown in FIG. 1B, and then field oxide film 3 for isolation of elements is selectively formed by LOCOS (local oxidation of silicon) selective oxidation. Then, gate oxide films 4 and 4a are formed by thermal oxidation and a polycrystalline silicon film is deposited on the whole surface. Phosphor, which is an N type impurity, is introduced into the polycrystalline silicon film by thermal diffusion, and then the polycrystalline silicon is selectively etched by photolithography to form gate electrodes 5 and 5a.
Subsequently, a source and a drain are formed. Ions of arsenic are selectively implanted into source-drain regions for an N channel FET, and then, the ions of boron are selectively implanted into source-drain regions for the P channel FET.
FIGS. 1A and 1B illustrate a source-drain forming step for an N channel FET, that is, an arsenic ion implanting step. In the prior art, photoresist 6 is so patterned that it is open only to the N channel FET region, that is, the arsenic ion implanting area 10 as shown in FIG. 1B.
An ion implanting step is carried out in the formation of an ohmic layer in a source-drain region according to the prior art when a wiring of a CMOS IS is formed, will be described with reference to FIG. 1C and FIG. 1D, which is a sectional view of FIG. 1C along the line A-B. Source 8, 8a and drain 9, 9a of a MCOS IC are formed. Subsequently, the interlayer insulating film 7 is formed, as shown in FIG. 1D, and then etched by photolithography to form contact holes for wiring.
Then, ions of phosphor are selectively implanted into the N channel FET area and ions of boron are selectively implanted into the P channel FET area in order to form ohmic layers in sources 8 and 8a and drains 9 and 9a.
FIGS. 1C and 1D illustrate an ohmic layer forming step for source 8a and drain 9a for a P channel FET, that is, a boron ion implanting step. In the prior art, photoresist 6 is so patterned that it is open only to contact holes 11a and 11b of the P channel FET into which ions of boron are to be implanted as shown in FIG. 1C.
Photoresist masks are used for selective ion implantation in the formation of a source-drain for an N channel FET and the formation of a source-drain for a P channel FET. Since photoresist is a high insulator, the surface potential thereof is raised by irradiation of charged particles such as ion implantation (the phenomenon will be hereinafter referred to as charge-up). For this reason, there arises a problem that when a high or medium concentration of ions is implanted for the formation of the source-drain region, the potential at the gate electrode is raised, exceeding the isolation voltage of a gate oxide film due to charge-up of a photoresist surface, thereby destroying the gate oxide film. Further, if ion implantation is performed through the opened photoresist in the case of the formation of the source-drain region, the surface of the photoresist is charged up, and moreover, since charge accumulated in the opening areas is not readily discharged, there is another problem in that the potential around the openings is raised so high that the gate oxide film may be broken. Also when an ohmic layer for formation of wiring to the source-drain areas is formed by ion implantation, the potential of the photoresist around the openings is similarly raised so high that a breakdown of the gate oxide film may occur.
Further, when the size of an opening decreases as miniaturization of the pattern of a semiconductor integrated circuit proceeds, a repulsive force may sometimes act upon the opening to break down the photoresist opening pattern due to the charge accumulated in the surface of the photoresist.